IA32

Also known as i386 or x86, the most common ISA on desktop machines for historical reasons. Recent implementations have many sophisticated features such as deep pipelines with out of order execution and good branch prediction.

• x86.org has links to the Intel architecture reference manauls.
• sandpile.org has information on the x86 architecture.
• The i386 SYSV Application Binary Interface specification.
• Technical documents from AMD.
• Documentation on optimizing for Pentium processors by Agner Fog.
• Assembly gems.
• The startup state of an ELF binary under Linux: process details, stack and register contents.
• Online drafts of the book Linkers and Loaders by John Levine: talks about object file formats, dynamic linking and loading, symbol management.

SPARC

The SPARC is a reduced instruction set architecture whose origins go back to the early work on RISC at Berkeley. Its original features include register windows and support for tagged arithmetic. Recent members of the family are 64 bit. Most SPARCS now have deep pipelines, but are in order.

• Sparc International have Architecture Manuals and Application Binary Interface specifications available for download.
• Whitepapers on the SPARC from Sun microelectronics.
• Information on the SPARC FPU units and their implementation of IEEE exceptions.
• An introduction to SPARC stacks and register windows.
• A description of the SPARC v8 architecture in Lambda-RTL, part of the Zephyr research project.
• A similar description from the MLRISC project.

Alpha

• Digital's Documentation Library.

MIPS

• MIPS publications.

PowerPC

• ABI on MacOS X
• Papers from Apple's Advanced Computation Group, in particular the paper on multiprecision arithmetic using Altivec.

Misc

• The New Jersey Machine-code toolkit aims to facilitate the development of applications which manipulate machine code, such as assemblers, code generators and debuggers. It allows the encoding and decoding of machine instructions symbolically, based on a compact specification of the target architecture (example description of the SPARC).
• MLRISC is a customizable optimizing back-end written in Standard ML.
• Papers published by the SUIF group at Stanford on advanced compilation techniques.
• Article on static instruction scheduling for dynamic issue processors.
• Research on binary translation: IBM's DAISY project. They dynamically translate PowerPC code to a VLIW instruction set, while introducing the maximum amount of instruction level parallelism.
• The C-- project aims to specify a portable assembly language which could serve as an intermediary between high-level compilers and retargeteable, optimizing code generators.
• The Memory Management reference.
• Papers on garbage collection, and the Memory Management Reference.
• Information on hardware performance counters, such as perfmon for UltraSPARC. See also the cpustat(1M) and cputrack(1) tools, the cpc library, and tracing(3TNF) in Solaris 8.
• Information on writing signal handling code from the Java GCC frontend.

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